In analog signal processing, output buffer amplifiers are needed for many applications, such as to drive earphones and loudspeakers in end-user telephone equipment. The demands made of an output buffer amplifier in that case include the capability of driving low-ohmic loads, sometimes with a high capacitive component, a large output signal rise up to near the operating voltage, adequate linearity without transfer distortion, and only slight quiescent current consumption. Conventional output buffer amplifiers are constructed as end stages of class AB in CMOS technology, and they have two drain-coupled complementary MOS transistors. The two MOS transistors are triggered by error or fault amplifiers, which are each fed back from the coupled drain terminals of the two MOS transistors to one input of the error amplifier. Such error amplifiers are known, for instance, from a paper by K. E. Brehmer and J. B. Wieser, entitled "Large Swing CMOS Power Amplifier", in IEEE Journal of Solid-State Circuits, Vol SC-18, No. 6, pp. 624-629, December 1983; a paper by B. K. Ahuja, P. R. Gray, W. M. Baxter and G. T. Uehara, entitled "A Programmable CMOS Dual-Channel Interface Processor for Telecommunications Applications", in IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 892-899, December 1984; and a paper by J. A. Fisher, entitled "A High-Performance CMOS Power Amplifier"- in IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 6 pp. 1200-1205, December, 1985.
The error or fault amplifier introduced by K. E. Brehmer and J. B. Wieser includes a symmetrically structured input differential amplifier stage with two source-coupled MOS transistors, which are connected to a supply potential through a current source. The drain terminals of the two MOS transistors are connected to the other supply potential through a current mirror circuit. The output of the input differential amplifier stage is carried to the gate terminal of an MOS output transistor located on the source side at the other supply potential, and to the source terminal of a further MOS transistor located on the gate side of the first supply potential. The drain terminal of the MOS output transistor is connected directly, and the drain terminal of the further MOS transistor is connected through an interposed capacitor, to the gate terminal of one of the two MOS transistors of the input differential stage. If the potential at the drain terminal of the MOS output transistor varies in the direction of the other supply potential, then the potential at the coupled source terminals of the two MOS transistors of the input differential stage shifts in the direction of the first supply potential, while the output of the input differential amplifier stage migrates in the direction of the second supply potential. As a result, one of the two MOS transistors of the input differential amplifier stage is already forced into the startup range at a medium control level, and the control level of the entire error amplifier is hindered as a result. The error amplifier therefore has only slight in-phase controllability.
It is accordingly an object of the invention to provide an error amplifier, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type.